The approaches described in this section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
A Time-to-Digital Converter (TDC) is an electronic device commonly used to measure a time interval between two events, namely the time between a start event and a stop event, and to convert it into a digital (binary) output value.
TDCs have become more and more popular in the circuit design community, and are used in an increasing number of applications for the design of various signal processing systems. For instance, in all-digital Phase-Locked Loops (PLL) used in frequency synthesizers, a TDC may serve as a phase detector. Other applications include TDC based Analog-to-Digital Converters (ADC).
Compared to original analog realizations that are based on a traditional approach that time-to-digital conversion is obtained by first converting the time interval into a voltage and then by digitizing this voltage by a conventional ADC, fully digital solutions are by far more robust.
For instance, the principle of operation of such fully digital solutions as counter based TDCs relies on the idea that the best solution to quantize a time interval is to count the cycles of a reference clock fitting into the interval. However, the interval to be measured is defined by the start and stop signals, which are completely asynchronous to the reference clock signal. This causes a measurement error at the beginning and at the end of the time interval. The measurement accuracy can be increased by using a higher clock frequency. However, increasing the clock frequency results in higher power consumption for the generation and processing of the clock signal.
Therefore, an alternative to the above counter based TDCs uses a digital delay-line. In such a digital delay-line based TDC, the start signal is fed into a delay-line comprising a chain of cascaded delay elements, such as logic gates connected in series. Thus, the start signal is delayed along the delay-line with each delay element generating a delayed version of the start signal. On the arrival of the stop signal, the delayed versions of the start signal are sampled in parallel. A thermometric-to-binary encoder then generates the digital binary TDC output value from the thermometric value defined by the set of samples. Either latches or flip-flops can be used as sampling elements. The resolution then depends on the delay of the delay elements in the chain.
The total noise from such a TDC is the sum of the quantization noise coming from its limited resolution and the analog jitter added at each transition of its logic gates.
In some applications, it is possible to use noise shaping techniques so that the quantization noise power is rejected towards high frequencies. This is particularly suited in the case of digital PLLs because the noise performance is ideally limited by the analog jitter sources only.
However, some quantization noise can still appear at low frequencies because of imperfect noise shaping.
As shown by the spectrum diagram of FIG. 1, which illustrates the power density L(f) at the output of a VCO as a function of the offset frequency f of the PLL, this can result in spurs 11 on the output spectrum when used in a digital PLL.
Dithering techniques can be used to avoid such problems and thus optimize the noise shaping performance.
A possible solution is to add digital noise at the output of the TDC encoder. This noise may be generated by pseudo random generators. An expected drawback of this solution, however, is that the added noise can be significantly stronger than the intrinsic analog performance of the TDC.
The present invention solves the disadvantages of the prior art by disclosing a device with analog dithering, for converting a time interval between an active edge of a first signal and an active edge of a second signal into a binary output value.
The present invention aims at providing an alternative solution for performing time-to-digital conversion with dithering.
Basically, the proposed solution is based on the observation that any delay-line based time-to-digital conversion mechanism consists in expressing a time difference as a number of propagation delays stemming from logic gates through which the start signal propagates until the stop signal occurs. Often, the TDC is built from logic gates whose propagation delay exhibits a dependency to the supply voltage. This is the case at least when standard logic gates are used. Thus, modulating the supply voltage will simultaneously modulate the conversion gain and introduce dithering into the conversion mechanism.